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lt3511 1 3511fb typical a pplica t ion fea t ures descrip t ion monolithic high voltage isolated flyback converter the lt ? 3511 is a high voltage monolithic switching regula- tor specifically designed for the isolated ?yback topology. no third winding or opto-isolator is required for regula- tion as the part senses output voltage directly from the primary-side ?yback waveform. the device integrates a 240ma, 150v power switch, high voltage circuitry, and control into a high voltage 16-lead msop package with four leads removed. the lt3511 operates from an input voltage range of 4.5v to 100v and delivers up to 2.5w of isolated output power. two external resistors and the transformer turns ratio easily set the output voltage. off-the-shelf transformers are available for several applications. the high level of integration and the use of boundary mode operation results in a simple, clean, tightly regulated application solution to the traditionally tough problem of isolated power delivery. output load and line regulation 48v to 5v isolated flyback converter a pplica t ions n 4.5v to 100v input voltage range n internal 240ma, 150v power switch n boundary mode operation n no transformer third winding or opto-isolator required for regulation n improved primary-side winding feedback load regulation n v out set with two external resistors n bias pin for internal bias supply and power switch driver n no external start-up resistor n 16-lead msop package n isolated telecom power supplies n isolated auxiliary/housekeeping power supplies n isolated industrial, automotive and medical power supplies l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5438499, 7471522. en/uvlo t c r fb r ref sw vc gnd bias lt3511 3511 ta01a 69.8k 16.9k v in 36v to 72v v out + 5v 0.3a v out ? 4:1 1m 1f 43.2k 19h 300h 22f 3.3nf 4.7f 10k 169k ? ? v in load current (ma) 0 4.75 v out (v) 4.85 4.95 5.05 50 100 150 200 3511 ta01b 250 5.15 5.25 4.80 4.90 5.00 5.10 5.20 300 v in = 36v v in = 72v v in = 48v
lt3511 2 3511fb a bsolu t e maxi m u m r a t ings sw (note 4) ............................................................ 150 v v in , en/uvlo .......................................................... 10 0v r fb ............................................................ 10 0v, v in 6v bias ................................................................... v in , 20v r ref , t c , vc ................................................................ 6v o perating junction temperature range (note 2) lt3511e, lt3511i ............................... C 40c to 125c lt3511h ............................................. C 40c to 150c lt3511mp .......................................... C 55c to 150c storage temperature range .................. C 65c to 150c (note 1) e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 24v unless otherwise noted. o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt3511ems#pbf lt3511ems#trpbf 3511 16-lead plastic msop C40c to 125c lt3511ims#pbf lt3511ims#trpbf 3511 16-lead plastic msop C40c to 125c lt3511hms#pbf lt3511hms#trpbf 3511 16-lead plastic msop C40c to 125c lt3511mpms#pbf lt3511mpms#trpbf 3511 16-lead plastic msop C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ p in c on f igura t ion 1 3 5 6 7 8 en/uvlo v in gnd bias nc gnd 16 14 12 11 10 9 sw r fb r ref t c vc gnd top view ms package 16(12)-lead plastic msop ja = 90c/w parameter conditions min typ max units input voltage range v in = bias l 6 4.5 100 15 v v quiescent current not switching v en/uvlo = 0.2v 2.7 0 3.5 ma a en/uvlo pin threshold en/uvlo pin voltage rising l 1.15 1.21 1.27 v en/uvlo pin current v en/uvlo = 1.1v v en/uvlo = 1.4v 2.0 2.6 0 3.3 a a maximum switching frequency 650 khz maximum current limit 240 330 430 ma minimum current limit 35 60 90 ma switch v cesat i sw = 100ma 0.3 v r ref voltage l 1.18 1.17 1.20 1.215 1.23 v v r ref voltage line regulation 6v < v in < 100v 0.01 0.03 %/v r ref pin bias current (note 3) l 80 400 na error amplifier voltage gain 150 v/v error amplifier transconductance ?i = 2a 140 mhos
lt3511 3 3511fb e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3511e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3511i is guaranteed to meet performance specifications from C40c to 125c operating junction temperature range. the lt3511h is guaranteed the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 24v unless otherwise noted. parameter conditions min typ max units minimum switching frequency 40 khz t c current into r ref r tc = 53.6k 9.5 a bias pin voltage internally regulated 3 3.1 3.2 v to meet performance specifications from C40c to 150c operating junction temperature range. the lt3511mp is guaranteed over the full C55c to 150c operating junction range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 3: current flows out of the r ref pin. note 4: the sw pin is rated to 150v for transients. operating waveforms of the sw pin should keep the pedestal of the flyback waveform below 100v as shown in figure 5. typical p er f or m ance c harac t eris t ics switch v cesat switch current limit quiescent current vs v in output voltage quiescent current bias pin voltage temperature (c) ?50 4.75 v out (v) 4.80 4.90 4.95 5.00 5.25 5.10 0 50 75 3511 g01 4.85 5.15 5.20 5.05 ?25 25 100 125 150 v in = 48v temperature (c) ?50 ?25 0 i q (ma) 2 5 0 50 75 3511 g02 1 4 3 25 100 125 150 v in = 24v v in = 48v v in = 100v temperature (c) ?50 2.0 bias voltage (v) 2.5 3.0 3.5 4.0 ?25 0 25 50 3511 g03 521 05100157 v in = 24v, 10ma v in = 24v, no load switch current (ma) 0 50 0 switch v cesat voltage (mv) 400 1000 100 200 250 3511 g04 200 800 600 150 300 350 temperature (c) ?50 current limit (ma) 350 25 3511 g05 200 100 ?25 0 50 50 0 400 300 250 150 521 05100157 minimum current limit maximum current limit voltage (v) 0 i q (ma) 2 3 80 3511 g06 1 0 20 40 60 100 4 t a = 25c, unless otherwise noted.
lt3511 4 3511fb typical p er f or m ance c harac t eris t ics maximum frequency vs temperature minimum frequency vs temperature en/uvlo shutdown threshold vs temperature boundary mode waveform light load discontinuous mode waveform en/uvlo pin (hysteresis) current vs temperature en/uvlo pin current vs v en/uvlo en/uvlo threshold vs temperature t a = 25c, unless otherwise noted. temperature (c) ?50 ?25 0 en/uvlo pin current (a) 2 5 0 50 75 3511 g07 1 4 3 25 100 521 0 51 en/uvlo = 1.2v temperature (c) ?50 en/uvlo threshold (v) 2.0 2.5 3.0 25 75 3511 g09 1.5 1.0 ?25 0 521 05100105 0.5 0 v en/uvlo voltage (v) 1 0 en/uvlo pin current (a) 5 10 15 20 25 30 20 40 60 80 3511 g08 100 temperature (c) ?50 ?25 0 maximum frequency (khz) 400 1000 0 50 75 3511 g10 200 800 600 25 100 521 051 temperature (c) ?50 ?25 0 minimum frequency (khz) 40 100 0 50 75 3511 g11 20 80 60 25 100 521 051 temperature (c) ?50 0 en/uvlo threshold (v) 0.1 0.3 0.4 0.5 50 0.9 3511 g14 0.2 0 ?25 75 100 25 521 051 0.6 0.7 0.8 20v/div 1s/div 3511 g12 20v/div 2s/div 3511 g13
lt3511 5 3511fb p in func t ions en/uvlo (pin 1): enable/undervoltage lockout. the en/ uvlo pin is used to start up the lt3511. pull the pin to 0v to shut down the lt3511. this pin has an accurate 1.21v threshold and can be used to program an undervoltage lockout (uvlo) threshold using a resistor divider from supply to ground. a 2.6a pin current hysteresis allows the programming of undervoltage lockout (uvlo) hys - teresis. en/uvlo can be directly connected to v in . if left open circuit the part will not power up. v in (pin 3): input supply pin. this pin supplies current to the internal start-up circuitry, and serves as a reference voltage for the dcm comparator and feedback circuitry. must be locally bypassed with a capacitor. gnd (pin 5, 8, 9): ground pins. all three pins should be tied directly to the local ground plane. bias (pin 6): bias voltage. this pin supplies current to the switch driver and internal circuitry of the lt3511. this pin may also be connected to v in if a third winding is not used and if v in < 20v. the part can operate down to 4.5v when bias and v in are connected together. if a third winding is used, the bias voltage should be lower than the input voltage and greater than 3.3v for proper operation. bias must be bypassed with a 4.7f capacitor placed close to the pin. vc (pin 10): compensation pin for internal error amplifier. connect a series rc from this pin to ground to compensate the switching regulator. an additional 100pf capacitor from this pin to ground helps eliminate noise. t c (pin 11): output voltage temperature compensa- tion. connect a resistor to ground to produce a current proportional to absolute temperature to be sourced into the r ref node. i tc = 0.55v/r tc . r ref (pin 12): input pin for external ground-referred reference resistor. the resistor at this pin should be 10k. for nonisolated applications, a traditional resistor voltage divider from v out may be connected to this pin. r fb (pin 14): input pin for external feedback resistor. this pin is connected to the transformer primary (v sw ). the ratio of this resistor to the r ref resistor, times the internal bandgap reference, determines the output voltage (plus the effect of any non-unity transformer turns ratio). for nonisolated applications, this pin should be connected to gnd with a 1m resistor. sw (pin 16): switch pin. collector of the internal power switch. minimize trace area at this pin to minimize emi and voltage spikes.
lt3511 6 3511fb b lock diagra m flyback error amp master latch current comparator bias r1 r2 r5 v out + v out ? v in t c bias sw v in v in gnd v1 120mv 1.2v v c d1 t1 n:1 i 2 r sense 0.02 c2 c1 l1a l1b r3 r4 c4 + ? internal reference and regulators oscillator tc current one shot r q s s g m + ? a1 + ? a5 + ? + ? a2 a4 3a + ? 3511 bd q2 r6 c3 q3 1.2v q4 q1 driver en/uvlo r fb r ref
lt3511 7 3511fb o pera t ion the lt3511 is a current mode switching regulator ic de- signed specifically for the isolated flyback topology. the key problem in isolated topologies is how to communicate information regarding the output voltage from the isolated secondary side of the transformer to the primary side. historically, opto-isolators or extra transformer windings communicate this information across the transformer. opto-isolator circuits waste output power, and the extra components increase the cost and physical size of the power supply. opto-isolators can also exhibit trouble due to limited dynamic response, nonlinearity, unit-to-unit variation and aging over life. circuits employing an extra transformer winding also exhibit deficiencies. using an extra winding adds to the transformers physical size and cost, and dynamic response is often mediocre. in the lt3511, the primary-side flyback pulse provides information about the isolated output voltage. in this man- ner, neither opto-isolator nor extra transformer winding is required for regulation. two resistors program the output voltage. since this ic operates in boundary mode, the part calculates output voltage from the switch pin when the secondary current is almost zero. the block diagram shows an overall view of the system. many of the blocks are similar to those found in traditional switching regulators including internal bias regulator, os- cillator, logic, current amplifier, current comparator, driver, and output switch. the novel sections include a special flyback error amplifier and a temperature compensation circuit. in addition, the logic system contains additional logic for boundary mode operation. the lt3511 features boundary mode control, where the part operates at the boundary between continuous con - duction mode and discontinuous conduction mode. the vc pin controls the current level just as it does in normal current mode operation, but instead of turning the switch on at the start of the oscillator period, the part turns on the switch when the secondary-side winding current is zero. boundary mode operation boundary mode is a variable frequency, current mode switching scheme. the switch turns on and the inductor current increases until a vc pin controlled current limit. after the switch turns off, the voltage on the sw pin rises to the output voltage divided by the secondary-to-primary transformer turns ratio plus the input voltage. when the secondary current through the diode falls to zero, the sw pin voltage falls below v in . a discontinuous conduction mode (dcm) comparator detects this event and turns the switch back on. boundary mode returns the secondary current to zero every cycle, so parasitic resistive voltage drops do not cause load regulation errors. boundary mode also allows the use of a smaller transformer compared to continuous conduction mode and does not exhibit subharmonic oscillation. at low output currents, the lt3511 delays turning on the switch, and thus operates in discontinuous mode. unlike traditional flyback converters, the switch has to turn on to update the output voltage information. below 0.6v on the vc pin, the current comparator level decreases to its minimum value, and the internal oscillator frequency decreases. with the decrease of the internal oscillator, the part starts to operate in dcm. the output current is able to decrease while still allowing a minimum switch off time for the flyback error amplifier. the typical minimum internal oscillator frequency with vc equal to 0v is 40khz.
lt3511 8 3511fb a pplica t ions i n f or m a t ion pseudo dc theory in the block diagram, r ref (r4) and r fb (r3) are external resistors used to program the output voltage. the lt3511 operates similar to traditional current mode switchers, except in the use of a unique error amplifier, which derives its feedback information from the flyback pulse. operation is as follows: when the output switch, q1, turns off, its collector voltage rises above the v in rail. the am- plitude of this flyback pulse, i.e., the difference between it and v in , is given as: v flbk = (v out + v f + i sec ? esr) ? nps v f = d1 forward voltage i sec = transformer secondary current esr = total impedance of secondary circuit nps = transformer effective primary-to-secondary turns ratio r fb and q2 convert the flyback voltage into a current. nearly all of this current flows through r ref to form a ground- referred voltage. the resulting voltage forms the input to the flyback error amplifier. the flyback error amplifier samples the voltage information when the secondary side winding current is zero. the bandgap voltage, 1.20v, acts as the reference for the flyback error amplifier. the relatively high gain in the overall loop will then cause the voltage at r ref to be nearly equal to the bandgap reference voltage v bg . the resulting relationship between v flbk and v bg approximately equals: v flbk r fb ? ? ? ? ? ? = v bg r ref or v flbk = v bg r fb r ref ? ? ? ? ? ? v bg = internal bandgap reference combination of the preceding expression with earlier derivation of v flbk results in the following equation: v out = v bg r fb r ref ? ? ? ? ? ? 1 n ps ? ? ? ? ? ? C v f C i sec esr ( ) the expression defines v out in terms of the internal ref - erence, programming resistors, transformer turns ratio and diode forward voltage drop. additionally, it includes the effect of nonzero secondary output impedance (esr). boundary control mode minimizes the effect of this im - pedance term. temperature compensation the first term in the v out equation does not have tem- perature dependence, but the diode forward drop has a significant negative temperature coefficient. a positive temperature coefficient current source connects to the r ref pin to compensate. a resistor to ground from the t c pin sets the compensation current. the following equation explains the cancellation of the temperature coefficient: v f t = C r fb r tc ? 1 n ps ? v tc t or, r tc = Cr fb n ps ? 1 v f / t ? v tc t r fb n ps ( v f / t ) = diodes forward voltage temperature coefficient (v tc / t ) = 2mv v tc = 0.55v experimentally verify the resulting value of r tc and adjust as necessary to achieve optimal regulation over temperature. the addition of a temperature coefficient current modifies the expression of output voltage as follows: v out = v bg r fb r ref ? ? ? ? ? ? 1 n ps ? ? ? ? ? ? C v f C v tc r tc ? ? ? ? ? ? ? r fb n ps C i sec esr ( ) output power a flyback converter has a complicated relationship be- tween the input and output current compared to a buck or a boost. a boost has a relatively constant maximum input current regardless of input voltage and a buck has a relatively constant maximum output current regardless of input voltage. this is due to the continuous nonswitching behavior of the two currents. a flyback converter has both discontinuous input and output currents which makes it
lt3511 9 3511fb a pplica t ions i n f or m a t ion similar to a nonisolated buck-boost. the duty cycle will affect the input and output currents, making it hard to predict output power. in addition, the winding ratio can be changed to multiply the output current at the expense of a higher switch voltage. the graphs in figures 1-4 show the typical maximum output power possible for the output voltages 3.3v, 5v, 12v and 24v. the maximum power output curve is the calculated output power if the switch voltage is 100v during the off- time. 50v of margin is left for leakage voltage spike. to achieve this power level at a given input, a winding ratio value must be calculated to stress the switch to 100v, resulting in some odd ratio values. the following curves are examples of common winding ratio values and the amount of output power at given input voltages. one design example would be a 5v output converter with a minimum input voltage of 36v and a maximum input voltage of 72v. a four-to-one winding ratio fits this design example perfectly and outputs close to 1.6w at 72v but lowers to 1w at 36v. the equations below calculate output power: power = ? v in ? d ? i peak ? 0.5 efficiency = = ~85% duty cycle = d = v out + v f ( ) ? n ps v out + v f ( ) ? n ps + v in peak switch current = i peak = 0.26a input voltage (v) 0 0 output power (w) 0.5 1.0 1.5 2.0 2.5 3.0 n = 1 5 20 40 60 80 3511 f01 100 n = 1 2 n = 1 0 n = 8 n = 6 n = 4 n = 2 n = n ps(max) input voltage (v) 0 0 output power (w) 0.5 1.0 1.5 2.0 2.5 3.0 20 40 60 80 3511 f02 100 n = 4 n = 5 n = 6 n = 7 n = 8 n = 3 n = 2 n = 1 n = n ps(max) input voltage (v) 0 0 output power (w) 0.5 1.0 1.5 2.0 2.5 3.0 20 40 60 80 3511 f04 100 n = 2 n = 1 n = n ps(max) figure 1. output power for 3.3v output figure 2. output power for 5v output figure 3. output power for 12v output figure 4. output power for 24v output input voltage (v) 0 0 output power (w) 0.5 1.0 1.5 2.0 2.5 3.5 3.0 20 40 60 80 3511 f03 100 n = 4 n = 5 n = 3 n = 2 n = 1 n = n ps(max)
lt3511 10 3511fb a pplica t ions i n f or m a t ion transformer design considerations successful application of the lt3511 relies on proper transformer specification and design. carefully consider the following information in addition to the traditional guidelines associated with high frequency isolated power supply transformer design. linear technology has worked with several leading mag - netic component manufacturers to produce pre-designed flyback transformers for use with the lt3511. table 1 shows the details of these transformers. table 1. predesigned transformers transformer part number l pri (h) leakage (h) n p :n s :n b isolation (v) saturation current (ma) vendor target applications 750311558 300 1.5 4:1:1 1500 500 wrth elektronik 48v to 5v, 0.3a 24v to 5v, 0.2a 12v to 5v, 0.13a 48v to 3.3v, 0.33a 24v to 3.3v, 0.28a 12v to 3.3v, 0.18a 750311019 400 5 6:1:2 1500 750 wrth elektronik 24v to 5v, 0.26a 12v to 5v, 0.17a 48v to 3.3v, 0.43a 24v to 3.3v, 0.35a 12v to 3.3v, 0.2a 750311659 300 2 1:1:0.2 1500 560 wrth elektronik 48v to 24v, 0.07a 750311660 350 3 2:1:0.33 1500 520 wrth elektronik 48v to 15v, 0.1a 48v to 12v, 0.12a 24v to 15v, 0.09a 12v to 15v, 0.045a 750311838 350 3 2:1:1 1500 520 wrth elektronik 48v to 15v, 0.05a 48v to 12v, 0.06a 24v to 15v, 0.045a 750311963 200 0.4 1:5:5 1500 650 wrth elektronik 12v to 70v, 0.004a 12v to 100v, 0.003a 12v to 150v, 0.002a 750311966 120 0.45 1:5:0.5 1500 900 wrth elektronik 12v to +120v and C12v, 0.002a 10396-t024 300 2.0 4:1:1 1500 500 sumida 48v to 5v, 0.3a 24v to 5v, 0.2a 12v to 5v, 0.13a 48v to 3.3v, 0.33a 24v to 3.3v, 0.28a 12v to 3.3v, 0.18a 10396-t026 300 2.5 6:1:2 1500 500 sumida 24v to 5v, 0.26a 12v to 5v, 0.17a 48v to 3.3v, 0.43a 24v to 3.3v, 0.35a 12v to 3.3v, 0.2a 01355-t057 250 2.0 1:1:0.2 1500 500 sumida 48v to 24v, 0.07a 10396-t022 300 2.0 2:1:0.33 1500 500 sumida 48v to 15v, 0.1a 48v to 12v, 0.12a 24v to 15v, 0.09a 12v to 15v, 0.045a 10396-t028 300 2.5 2:1:1 1500 500 sumida 48v to 15v, 0.05a 48v to 12v, 0.06a 24v to 15v, 0.045a
lt3511 11 3511fb a pplica t ions i n f or m a t ion turns ratio note that when using an r fb /r ref resistor ratio to set output voltage, the user has relative freedom in selecting a transformer turns ratio to suit a given application. in contrast, the use of simple ratios of small integers, e.g., 1:1, 2:1, 3:2, provides more freedom in setting total turns and mutual inductance. typically, choose the transformer turns to maximize avail - able output power. for low output voltages (3.3v or 5v), a n:1 turns ratio can be used with multiple primary windings relative to the secondary to maximize the transformers current gain (and output power). however, remember that the sw pin sees a voltage that is equal to the maximum input supply voltage plus the output voltage multiplied by the turns ratio. in addition, leakage inductance will cause a voltage spike (v leakage ) on top of this reflected voltage. this total quantity needs to remain below the absolute maximum rating of the sw pin to prevent breakdown of the internal power switch. together these conditions place an upper limit on the turns ratio, n, for a given application. choose a turns ratio low enough to ensure: n < 150v C v in(max) C v leakage v out + v f for larger n:1 values, choose a transformer with a larger physical size to deliver additional current. in addition, choose a large enough inductance value to ensure that the off-time is long enough to measure the output voltage. for lower output power levels, choose a 1:1 or 1:n trans- former for the absolute smallest transformer size. a 1:n transformer will minimize the magnetizing inductance (and minimize size), but will also limit the available output power. a higher 1:n turns ratio makes it possible to have very high output voltages without exceeding the breakdown voltage of the internal power switch. the turns ratio is an important element in the isolated feedback scheme. make sure the transformer manufacturer guarantees turns ratio accuracy within 1%. saturation current the current in the transformer windings should not ex - ceed its rated saturation current. energy injected once the core is saturated will not be transferred to the secondary and will instead be dissipated in the core. information on saturation current should be provided by the transformer manufacturers. table 1 lists the saturation current of the transformers designed for use with the lt3511. primary inductance requirements the lt3511 obtains output voltage information from the reflected output voltage on the switch pin. the conduction of secondary winding current reflects the output voltage on the primary. the sampling circuitry needs a minimum of 400ns to settle and sample the reflected output voltage. in order to ensure proper sampling, the secondary winding needs to conduct current for a minimum of 400ns. the following equation gives the minimum value for primary- side magnetizing inductance: l pri t off(min) ? n ps ? v out + v f ( ) i peak(min) t off(min) = 400ns i peak(min) = 55ma in addition to the primary inductance requirement for sampling time, the lt3511 has internal circuit constraints that prevent the switch from staying on for less than 100ns. if the inductor current exceeds the desired current limit during that time, oscillation may occur at the output as the current control loop will lose its ability to regulate. the following equation, based on maximum input voltage, must also be followed in selecting primary-side magnetiz - ing inductance: l pri t on(min) ? v in(max) i peak(min) t on(min) = 100ns i peak(min) = 55ma
lt3511 12 3511fb leakage inductance and clamp circuits transformer leakage inductance (on either the primary or secondary) causes a voltage spike to appear at the primary after the output switch turns off. this spike is increasingly prominent at higher load currents where more stored en - ergy must be dissipated. when designing an application, adequate margin should be kept for the effect of leakage voltage spikes. in most cases the reflected output voltage on the primary plus v in should be kept below 100v. this leaves at least 50v of margin for the leakage spike across line and load conditions. a larger voltage margin will be needed for poorly wound transformers or for excessive leakage inductance. figure 5 illustrates this point. minimize transformer leakage inductance. a clamp circuit is recommended for most applications. two circuits that can protect the internal power switch include the rcd (resistor-capacitor-diode) clamp and the dz (diode-zener) clamp. the clamp circuits dissipate the stored energy in the leakage inductance. the dz clamp is the recommended clamp for the lt3511. simplicity of design, high clamp voltages, and low power levels make the dz clamp the preferred solution. additionally, a dz clamp ensures well defined and consistent clamping voltages. figure 5 shows the clamp effect on the switch waveform and figure 6 shows the connection of the dz clamp. <100v <140v <150v v sw t off > 400ns with clamp time t sp < 150ns 3511 f05 <100v <150v v sw v leakage t off > 400ns without clamp time t sp < 150ns figure 5. maximum voltages for sw pin flyback waveform 3511 f06 l s d z figure 6. dz clamp proper care must be taken when choosing both the diode and the zener diode. schottky diodes are typically the best choice, but some pn diodes can be used if they turn on fast enough to limit the leakage inductance spike. choose a diode that has a reverse-voltage rating higher than the maximum switch voltage. the zener diode breakdown voltage should be chosen to balance power loss and switch voltage protection. the best compromise is to choose the largest voltage breakdown. use the following equation to make the proper choice: v zener(max) 150v C v in(max) for an application with a maximum input voltage of 72v, choose a 68v v zener which has v zener(max) at 72v, which will be below the 78v maximum. the power loss in the clamp will determine the power rat - ing of the zener diode. power loss in the clamp is highest a pplica t ions i n f or m a t ion
lt3511 13 3511fb at maximum load and minimum input voltage. the switch current is highest at this point along with the energy stored in the leakage inductance. a 0.5w zener will satisfy most applications when the highest v zener is chosen. choosing a low value for v zener will cause excessive power loss as shown in the following equations: dz power loss = 1 2 ? l ? i pk(vin(min)) 2 ? f sw ? 1+ n ps ? v out + v f ( ) v zener C n ps ? v out + v f ( ) ? ? ? ? ? ? ? ? l = leakage inductance i pk(vin(min)) = v out ? i out ? 2 ? v in(min) ? d vin(min) f sw = 1 t on + t off = 1 l pri ? i pk(vin(min)) v in(min) + l pri ? i pk(vin(min)) n ps ? v out + v f ( ) tables 2 and 3 show some recommended diodes and zener diodes. table 2. recommended zener diodes part v zener (v) power (w) case vendor mmsz5266bt1g 68 0.5 sod-123 on semi mmsz5270bt1g 91 0.5 sod-123 cmhz5266b 68 0.5 sod-123 central semiconductor cmhz5267b 75 0.5 sod-123 bzx84j-68 68 0.5 sod323f nxp bzx100a 100 0.5 sod323f table 3. recommended diodes part i (a) v reverse (v) case vendor bav21w 0.625 200 sod-123 diodes inc. bav20w 0.625 150 sod-123 leakage inductance blanking when the power switch turns off, the flyback pulse appears. however, a finite time passes before the trans - former primary-side voltage waveform approximately represents the output voltage. rise time on the sw node and transformer leakage inductance cause the delay . the leakage inductance also causes a very fast voltage spike on the primary side of the transformer. the amplitude of the leakage spike is largest when power switch current is highest. introduction of an internal fixed delay between switch turn-off and the start of sampling provides immunity to the phenomena discussed above. the lt3511 sets internal blanking to 150ns. in certain cases leakage inductance spikes last longer than the internal blanking, but will not signifi - cantly affect output regulation. secondary leakage inductance in addition to primary leakage inductance, secondary leakage inductance exhibits an important effect on ap- plication design. secondary leakage inductance forms an inductive divider on the transformer secondary. the inductive divider effectively reduces the size of the primary-referred flyback pulse. the smaller flyback pulse results in a higher regulated output voltage. the inductive divider effect of secondary leakage inductance is load independent. r fb /r ref ratio adjustments can ac- commodate this effect to the extent secondary leakage inductance is a constant percentage of mutual inductance (over manufacturing variations). winding resistance effects resistance in either the primary or secondary will re - duce overall efficiency (p out /p in ). good output voltage regulation will be maintained independent of winding resistance due to the boundary mode operation of the lt3511. bifilar winding a bifilar, or similar winding technique, is a good way to minimize troublesome leakage inductances. however, re - member that this will also increase primary-to-secondary capacitance and limit the primary-to-secondary breakdown voltage, so bifilar winding is not always practical. the linear technology applications group is available and extremely qualified to assist in the selection and/or design of the transformer. a pplica t ions i n f or m a t ion
lt3511 14 3511fb application design considerations iterative design process the lt3511 uses a unique sampling scheme to regulate the isolated output voltage. the use of this isolated scheme requires a simple iterative process to choose feedback resistors and temperature compensation. feedback re- sistor values and temperature compensation resistance is heavily dependent on the application, transformer and output diode chosen. once resistor values are fixed after iteration, the values will produce consistent output voltages with the chosen transformer and output diode. remember, the turns ratio of the transformer must be guaranteed within 1%. the transformer vendors mentioned in this data sheet can build transformers to this specification. selecting r fb and r ref resistor values the following section provides an equation for setting r fb and r ref values. the equation should only serve as a guide. follow the procedure outlined in the design procedure to set accurate values for r fb , r ref and r tc using the iterative design procedure. rearrangement of the expression for v out in the tempera - ture compensation section, developed in the operations section, yields the following expression for r fb : r fb = r ref ? n ps v out + v f ( ) + v tc ? ? ? ? v bg where: v out = output voltage v f = switching diode forward voltage n ps = effective primary-to-secondary turns ratio v tc = 0.55v this equation assumes: r tc = r fb n ps the equation assumes the temperature coefficients of the diode and v tc are equal, which is a good first order approximation. strictly speaking, the above equation defines r fb not as an absolute value, but as a ratio of r ref . so the next question is, what is the proper value for r ref ? the answer is that r ref should be approximately 10k. the lt3511 is trimmed and specified using this value of r ref . if the impedance of r ref varies considerably from 10k, additional errors will result. however, a variation in r ref of several percent is acceptable. this yields a bit of freedom in selecting stan- dard 1% resistor values to yield nominal r fb /r ref ratios. undervoltage lockout (uvlo) a resistive divider from v in to the en/uvlo pin imple- ments undervoltage lockout (uvlo). figure 7 shows this configuration. the en/uvlo pin threshold is set at 1.21v. in addition, the en/uvlo pin draws 2.6a when the volt- age at the pin is below 1.21v. this current provides user programmable hysteresis based on the value of r1. the effective uvlo thresholds are: v in(uvlo,rising) = 1.2v ? r1 + r2 ( ) r2 + 2.6a ? r1 v in(uvlo,falling) = 1.2v ? r1 + r2 ( ) r2 figure 7 also shows the implementation of external shut - down control while still using the uvlo function. the nmos grounds the en/uvlo pin when turned on, and puts the lt3511 in shutdown with quiescent current draw of less than 1a. lt3511 en/uvlo gnd r2 r1 v in 3511 f07 run/stop control (optional) figure 7. undervoltage lockout (uvlo) a pplica t ions i n f or m a t ion
lt3511 15 3511fb minimum load requirement the lt3511 recovers output voltage information using the flyback pulse. the flyback pulse occurs once the switch turns off and the secondary winding conducts current. in order to regulate the output voltage, the lt3511 needs to sample the flyback pulse. the lt3511 delivers a minimum amount of energy even during light load conditions to ensure accurate output voltage information. the minimum delivery of energy creates a minimum load requirement of 10ma to 15ma depending on the specific application. verify minimum load requirements for each application. a zener diode with a zener breakdown of 20% higher than the output voltage can serve as a minimum load if pre-loading is not acceptable. for a 5v output, use a 6v zener with cathode connected to the output. bias pin considerations the bias pin powers the internal circuitry of the lt3511. three unique configurations exist for regulation of the bias pin. in the first configuration, the internal ldo drives the bias pin internally from the v in supply. in the second setup, the v in supply directly drives the bias pin through a direct connection bypassing the internal ldo. this configuration will allow the part to operate down to 4.5v and up to 15v. in the third configuration, an external supply or third wind- ing drives the bias pin. use this option when a voltage supply exists lower than the input supply. drive the bias pin with a voltage supply higher than 3.3v to disable the internal ldo. the lower voltage supply provides a more efficient source of power for internal circuitry. overdriving the bias pin with a third winding the lt3511 provides excellent output voltage regulation without the need for an opto-coupler, or third winding, but for some applications with higher input voltages (>20v), an additional winding (often called a third winding) im- proves overall system efficiency. design the third winding to output a voltage between 3.3v and 12v. for a typical 48v in application, overdriving the bias pin improves ef - ficiency 4% to 5%. lt3511 3.3v < bias < 20v 6v to 100v bias v in 3511 f08 external supply ldo lt3511 3v 6v to 100v bias v in ldo lt3511 4.5v to 15v bias v in optional ldo figure 8. bias pin configurations loop compensation an external resistor-capacitor network compensates the lt3511 on the vc pin. typical compensation values are in the range of r c = 20k and c c = 2.2nf (see the numerous schematics in the typical applications section for other pos - sible values). proper choice of both r c and c c is important to achieve stability and acceptable transient response. for example, vulnerability to high frequency noise and jitter result when r c is too large. on the other hand, if r c is too small, transient performance suffers. the inverse is true with respect to the value of c c . transient response suffers with too large of a c c , and instability results from too small a c c . the specific value for r c and c c will vary based on the application and transformer choice. verify specific choices with board level evaluation and transient response performance. a pplica t ions i n f or m a t ion
lt3511 16 3511fb design procedure/design example use the following design procedure as a guide to design- ing applications for the lt3511. remember, the unique sampling architecture requires an iterative process for choosing correct resistor values. the design example involves designing a 15v output with a 100ma load current and an input range from 36v to 72v. v in(min) = 36v, v in(nom) = 48v, v in(max) = 72v, v out = 15v and i out = 100ma step 1: select the transformer turns ratio. n ps < v sw(max) C v in(max) C v leakage v out + v f v sw(max) = max rating of internal switch = 150v v leakage = margin for transformer leakage spike = 40v v f = forward voltage of output diode = assume approxi - mately ~ 0.5v example: n ps < 150v C 72v C 40v 15v + 0.5v n ps < 2.45 n ps = 2 the choice of turns ratio is critical in determining output power as shown earlier in the output power section. at this point, a third winding can be added to the transformer to drive the bias pin of the lt3511 for higher efficiencies. choose a turns ratio that sets the third winding voltage to regulate between 3.3v and 6v for maximum efficiency. choose a third winding ratio to drive bias winding with 5v. (optional) example: n third n s = v third v out = 5v 15v = 0.33 the turns ratio of the transformer chosen is as follows n primary : n secondary : n third = 2:1:0.33. step 2: calculate maximum power output at minimum v in . p out(vin(min)) = ? v in(min) ? i in = ? v in(min) ? d ? i peak ? 0.5 d = v out + v f ( ) ? n ps v out + v f ( ) ? n ps + v in(min) = efficiency = ~75% i peak = peak switch current = 0.26a example: d = 0.46 p out(vin(min)) = 1.62 i out(vin(min)) = p out(vin(min)) /v out = 0.11a the chosen turns ratio satisfies the output current re- quirement of 100ma. if the output current was too low, the minimum input voltage could be adjusted higher. the turns ratio in this example is set to its highest ratio given switch voltage requirements and margin for leakage in- ductance voltage spike. step 3: determine primary inductance, switching fre- quency and saturation current. primary inductance for the transformer must be set above a minimum value to satisfy the minimum off and on time requirements. l pri t off(min) ? n ps ? v out + v f ( ) i peak(min) t off(min) = 400ns i peak(min) = 55ma l pri t on(min) ? v in(max) i peak(min) t on(min) = 100ns i peak(min) = 55ma a pplica t ions i n f or m a t ion
lt3511 17 3511fb example: l pri 400ns ? 2 ? 15 + 0.5 ( ) 0.055 l pri 225h l pri 100ns ? 72 0.055 l pri 131h in addition, primary inductance will determine switching frequency . f sw = 1 t on + t off = 1 l pri ? i peak v in + l pri ? i peak n ps ? v out + v f ( ) i peak = v out ? i out ? 2 ? v in ? d example: lets calculate switching frequency at our nominal v in of 48v. d = 15 + 0.5 ( ) ? 2 15 + 0.5 ( ) ? 2 + 48 = 0.39 i peak = 15v ? 0.1a ? 2 0.75 ? 48v ? 0.39 = 0.21a lets choose l pri = 350h. remember, most transform- ers specify primary inductance with a tolerance of 20%. f sw = 256khz finally, the transformer needs to be rated for the correct saturation current level across line and load conditions. in the given example, the worst-case condition for switch current is at minimum v in and maximum load. i peak = v out ? i out ? 2 ? v in ? d i peak = 15v ? 0.1a ? 2 0.75 ? 36v ? 0.46 = 0.24a ensure that the saturation current covers steady-state operation, start-up and transient conditions. to satisfy these conditions, choose a saturation current 50% or more higher than the steady-state calculation. in this example, a saturation current between 400ma and 500ma is chosen. table 1 presents a list of pre-designed flyback transform - ers. for this application, the wrth 750311660 transformer will be used. step 4: choose the correct output diode. the two main criteria for choosing the output diode include forward current rating and reverse voltage rating. the maximum load requirement is a good first-order guess at the average current requirement for the output diode. a better metric is rms current. i rms = i peak(vin(min)) ? n ps ? 1C d vin(min) 3 example: i rms = 0.24 ? 2 ? 1C 0.46 3 = 0.2a next calculate reverse voltage requirement using maxi- mum v in : v reverse = v out + v in(max) n ps example: v reverse = 15v + 72v 2 = 51v a 0.5a, 60v diode from diodes inc. (sbr0560s1) will be used. step 5: choose an output capacitor. the output capacitor choice should minimize output voltage ripple and balance the trade-off between size and cost for a larger capacitor. use the equation below at nominal v in : c = i out ? d ? v out ? f sw a pplica t ions i n f or m a t ion
lt3511 18 3511fb example: design for ripple levels below 50mv. c = 0.1a ? 0.39 0.05v ? 256khz = 3.1f a 10f, 25v output capacitor is chosen. remember ce - ramic capacitors lose capacitance with applied voltage. the capacitance can drop to 40% of quoted capacitance at the max voltage rating. step 6: design clamp circuit. the clamp circuit protects the switch from leakage induc - tance spike. a dz clamp is the preferred clamp circuit. the zener and the diode need to be chosen. the maximum zener value is set according to the maxi- mum v in : v zener(max) 150v C v in(max) example: v zener(max) 150v C 72v v zener(max) 78v in addition, power loss in the clamp circuit is inversely related to the clamp voltage as shown previously. higher clamp voltages lead to lower power loss. a 68v zener with a maximum of 72v will provide optimal protection and minimize power loss. half-watt zeners will satisfy most clamp applications involving the lt3511. power loss can be calculated using the equations presented in the leakage inductance and clamp circuit section. the zener chosen is a 68v 0.5w zener from on semicon- ductor (mmsz5266bt1g). choose a diode that is fast and has sufficient reverse voltage breakdown: v reverse > v sw(max) v sw(max) = v in(max) + v zener(max) example: v reverse > 140v the diode needs to handle the peak switch current of the switch which was determined to be 0.24a. a 200v, 0.6a diode from diodes inc. (bav21w) is chosen. step 7: compensation. compensation will be optimized towards the end of the de- sign procedure. connect a resistor and capacitor from the vc node to ground. use a 20k resistor and a 2.2nf capacitor. step 8: select r fb and r tc resistors. use the following equations to choose starting values for r fb and r tc . set r ref to 10k. r fb = v out + v f + 0.55v ( ) ? n ps ? r ref 1.2v r ref = 10k r tc = r fb n ps example: r fb = 15 + 0.5 + 0.55v ( ) ? 2 ? 10k 1.2v = 267k r tc = 267k 2 = 133k step 9: adjust rfb based on output voltage. power up the application with application components connected and measure the regulated output voltage. readjust r fb based on the measured output voltage. r fb(new) = v out v out(meas) ? r fb(old) example: r fb(new) = 15v 16.8v ? 267k = 237k step 10: remove r tc and measure output voltage over temperature. measure output voltage in a controlled temperature envi- ronment like an oven to determine the output temperature coefficient. measure output voltage at a consistent load current and input voltage, across the temperature range of operation. this procedure will optimize line and load regulation over temperature. a pplica t ions i n f or m a t ion
lt3511 19 3511fb calculate the temperature coefficient of v out : ? v out ? temp = v out(hot) C v out(cold) t hot( c) C t cold( c) example: v out measured at 100ma and 48v in ? v out ? temp = 15.70v C 15.37v 125 c C C50 c ( ) = 1.9mv/ c step 11: calculate new value for r tc . r tc(new) = r fb n ps ? 1.85mv / c ? v out ? temp example: r tc(new) = 237k 2 ? 1.85 1.9 = 118k step 12: place new value for r tc , measure v out , and readjust r fb due to r tc change. r fb(new) = v out v out(meas) ? r fb(old) example: r fb(new) = 15v 15v ? 237k = 237k step 13: verify new values of r fb and r tc over temperature. measure output voltage over temperature with r tc connected. step 14: optimize compensation. now that values for r fb and r tc are fixed, optimize the compensation. compensation should be optimized for transient response to load steps on the output. check transient response across the load range. example: the optimal compensation for the application is: r c = 22.1k, c c = 4.7nf step 15: ensure minimum load. check minimum load requirement at maximum input voltage. the minimum load occurs at the point where the output voltage begins to climb up as the converter delivers more energy than what is consumed at the output. example: the minimum load at an input voltage of 72v is: 7ma step 16: en/uvlo resistor values. determine amount of hysteresis required. voltage hysteresis = 2.6a ? r1 example: choose 2v of hysteresis. r1 = 2v 2.6a = 768k determine uvlo threshold. v in(uvlo,falling) = 1.2v ? r1 + r2 ( ) r2 r2 = 1.2v ? r1 v in(uvlo,falling) C 1.2v set uvlo falling threshold to 30v. r2 = 1.2v ? 768k 30v C 1.2v = 32.4k v in(uvlo,falling) = 1.2v ? r1 + r2 ( ) r2 = 1.2v ? 768k + 32.4k ( ) 32.4k = 30v v in(uvlo,rising) = v in(uvlo,falling) + 2.6a ? r1 = 30v + 2.6a ? 768k = 32v a pplica t ions i n f or m a t ion
lt3511 20 3511fb typical a pplica t ions 48v to 5v isolated flyback converter 48v to 15v isolated flyback converter 3511 ta02 r5 69.8k v in 36v to 72v v out + 5v 0.3a v out ? 4:1:1 d1 r1 1m r2 43.2k c1 1 f c4 22 f t1 300 h 19 h c1: taiyo yuden hmk316b7105kl-t c3: taiyo yuden emk212b7475kg c4: murata grm32er71c226ke18b d1, d2: diodes inc. sbr140s3 d3: diodes inc. bav21w t1: wrth 750311558 z1: on semi mmsz5266bt1g r4 10k r3 169k r6 16.9k optional third winding for hv operation c2 3.3nf c3 4.7f l1c 19h d3 z1 d2 en/uvlo tc vc gnd bias lt3511 v in sw r fb r ref 3511 ta03 r5 97.6k v in 36v to 72v v out + 15v 0.1a v out ? 2:1 d1 r1 1m r2 43.2k c1 1 f c4 10 f t1 350 h 88 h r4 10k r3 237k r6 13k c2 6.8nf c3 4.7f d2 z1 en/uvlo t c vc gnd bias lt3511 v in sw r fb r ref c1: taiyo yuden hmk316b7105kl-t c3: taiyo yuden emk212b7475kg c4: murata grm31cr71e106ka12 d1: diodes inc. sbr0560s1 d2: diodes inc. bav21w t1: wrth 750311660 z1: on semi mmsz5266bt1g
lt3511 21 3511fb typical a pplica t ions 24v to 5v isolated flyback converter 48v to 24v isolated flyback converter 3511 ta04 r5 200k v in 36v to 72v v out + 24v 65ma v out ? 1:1 d1 r1 1m r2 43.2k c1 1 f c4 4.7 f t1 300 h 300 h r4 10k r3 187k r6 33.2k c2 3.3nf c3 4.7f d2 z1 en/uvlo t c vc gnd bias lt3511 v in sw r fb r ref c1: taiyo yuden hmk316b7105kl-t c3: taiyo yuden emk212b7475kg c4: murata grm32er71h475ka88b d1: diodes inc. sbr1u150sa d2: diodes inc. bav21w t1: wrth 750311659 z1: on semi mmsz5266bt1g 3511 ta05 r5 73.2k v in 20v to 30v v out + 5v 0.25a v out ? 6:1 d1 r1 1m r2 80.6k c1 4.7 f c4 22 f t1 300 h 8 h r4 10k r3 249k r6 9.31k c2 15nf c3 4.7f d2 z1 en/uvlo t c vc gnd bias lt3511 v in sw r fb r ref c1: murata grm31cr71h475ka12b c3: taiyo yuden emk212b7475kg c4: murata grm32er71c226ke18b d1: diodes inc. sbr2a30p1 d2: diodes inc. bav20w t1: sumida 10396-t026 z1: on semi mmsz5270bt1g
lt3511 22 3511fb typical a pplica t ions 24v to 15v isolated flyback converter 12v to 15v isolated flyback converter 3511 ta06 r5 133k v in 20v to 30v v out + 15v 0.09a v out ? 2:1 d1 r1 1m r2 80.6k c1 4.7 f c4 10 f t1 350 h 88 h r4 10k r3 237k r6 20k c2 4.7nf c3 4.7f d2 z1 en/uvlo t c vc gnd bias lt3511 v in sw r fb r ref c1: murata grm31cr71h475ka12b c3: taiyo yuden emk212b7475kg c4: murata grm31cr71e106ka12b d1: diodes inc. sbr140s3 d2: diodes inc. bav20w t1: wrth 750311660 z1: on semi mmsz5270bt1g 3511 ta08 r5 133k v in 8v to 20v v out + 15v 40ma v out ? 2:1 d1 optional minimum load r1 1m r2 562k c1 4.7 f c4 4.7 f t1 350 h 88 h r4 10k r3 237k r6 26.1k c2 4.7nf c3 4.7f d2 z1 z2 en/uvlo t c vc gnd bias lt3511 v in sw r fb r ref c1: murata grm31cr71h475ka12b c3: taiyo yuden emk212b7475kg c4: murata grm31cr71h475ka12 d1: diodes inc. sbr130s3 d2: diodes inc. bav20w t1: wrth 750311660 z1: on semi mmsz5270bt1g
lt3511 23 3511fb 12v to 70v isolated flyback converter 48v to 3.3v non-isolated flyback converter 48v to 12v isolated flyback converter 3511 ta07 r5 191k v in 8v to 20v v out1 + 70v 4ma v out1 ? 1:5:5 d1 r1 1m r2 562k c1 2.2 f c4 0.47f c5 0.47f t1 80 h r4 10k r3 105k r6 90k c2 6.8nf c3 4.7f d3 z1 v out2 + 4ma v out2 ? ?70v d2 en/uvlo t c vc gnd bias lt3511 v in sw r fb r ref c1: murata grm21br71e225ka73b c3: taiyo yuden emk212b7475kg c4, c5: nippon chemi-con kts251b474m43n0t00 d1, d2: central semi crm1u-06m d3: diodes inc. bav20w t1: wrth 750311692 z1: nxp bzx100a 3511 ta09 r5 1m v in 36v to 72v v out 3.3v 0.4a v out ? 6:1 d1 r1 1m r2 43.2k c1 1 f c4 47 f t1 400 h 11 h r4 5k r3 1m r6 8k c2 4.7nf c3 4.7f d2 v out 8.66k en/uvlo t c vc gnd bias lt3511 v in sw r fb r ref z1 c1: taiyo yuden hmk316b7105kl-t c3: taiyo yuden emk212b7475kg c4: taiyo yuden lmk325b7476mm-tr d1: diodes inc. sbr2a30p1 d2: diodes inc. bav21w t1: wrth 750311019 z1: on semi mmsz5266bt1g 3511 ta10 r5 143k v in 36v to 72v v out + 12v 0.1a v out ? 2:1 d1 r1 1m r2 43.2k c1 1 f c4 4.7 f t1 300 h 75 h r4 10k r3 191k r6 15k c2 6.8nf c3 4.7f d2 en/uvlo t c vc gnd bias lt3511 v in sw r fb r ref z1 c1: taiyo yuden hmk316b7105kl-t c3: taiyo yuden emk212b7475kg c4: murata grm31cr71h475ka12 d1: diodes inc. sbr0560s1 d2: diodes inc. bav21w t1: sumida 10396-t022 z1: on semi mmsz5266bt1g typical a pplica t ions
lt3511 24 3511fb p ackage descrip t ion ms package variation: ms16 (12) 16-lead plastic msop with 4 pins removed (reference ltc dwg # 05-08-1847 rev a) msop (ms12) 0510 rev a 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 1.0 (.0394) bsc 0.50 (.0197) bsc 16 14 121110 1 3 5 6 7 8 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 1.0 (.0394) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006)
lt3511 25 3511fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 4/11 added mp-grade. revised r fb pin description in the pin functions section. updated efficiency equation and table 1 in the applications information section. revised the typical applications drawings. 2, 3 5 9, 10 20, 21 b 6/11 deleted text from turns ratio section and added text to primary inductance requirements of applications information 11 minor edit to text and revision to table 3 in leakage inductance and clamp circuits section of applications information 12-13 replaced step 3 in design procedure/design example section of applications information 16 revised equation and made minor text edit to step 6 in design procedure/design example section of applications information 18 updated d2: diodes part numbers in all typical applications 20-23, 26 added lt3512 to related parts section 26
lt3511 26 3511fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0611 rev b ? printed in usa r ela t e d p ar t s typical a pplica t ion 48v to 15v isolated flyback converter 3511 ta11 r5 154k v in 36v to 72v v out1 + 15v 50ma v out1 ? 2:1:1 d1 r1 1m r2 43.2k c1 1 f c4 4.7 f t1 350 h 88 h r4 10k r3 237k r6 20k c2 6.8nf c3 4.7f d3 v out2 + 50ma v out2 ? ?15v d2 c5 4.7 f 88 h en/uvlo t c vc gnd bias lt3511 v in sw r fb r ref z1 c1: taiyo yuden hmk316b7105kl-t c3: taiyo yuden emk212b7475kg c4, c5: murata grm31cr71h475ka12 d1, d2: diodes inc. sbr0560s1 d3: diodes inc. bav21w t1: wrth 750311838 z1: central semi cmhz5266b part number description comments lt3512 monolithic high voltage, isolated flyback converter, no opto-coupler required 4.5v v in 100v, 420ma/150v onboard power switch, msop-16(12) with high voltage pin spacing lt3958 high input voltage boost, flyback, sepic and inverting converter 5v v in 80v, 3.3a/84v onboard power switch, 5mm u 6mm qfn-36 with high voltage pin spacing lt3748 100v isolated flyback controller 5v v in 100v, no opto-isolator or third winding required, onboard gate driver, msop-16 with high voltage pin spacing lt3957 boost, flyback, sepic and inverting converter 3v v in 40v, 5a/40v onboard power switch, 5mm u 6mm qfn-36 with high voltage pin spacing lt3956 constant-current, constant-voltage boost, buck, buck-boost, sepic or flyback converter 4.5v v in 80v, 3.3a/84v onboard power switch, true pwm dimming, 5mm u 6mm qfn-36 with high voltage pin spacing lt3575 isolated flyback switching regulator with 60v/2.5a integrated switch 3v v in 40v, no opto-isolator or third winding required, up to 14w, tssop-16e lt3573 isolated flyback switching regulator with 60v/1.25a integrated switch 3v v in 40v, no opto-isolator or third winding required, up to 7w, msop-16e lt3574 isolated flyback switching regulator with 60v/0.65a integrated switch 3v v in 40v, no opto-isolator or third winding required, up to 3w, msop-16 lt3757 boost, flyback, sepic and inverting controller 2.9v v in 40v, 100khz to 1mhz programmable operating frequency, 3mm u 3mm dfn-10 and msop-10e package lt3758 boost, flyback, sepic and inverting controller 5.5v v in 100v, 100khz to 1mhz programmable operating frequency, 3mm u 3mm dfn-10 and msop-10e package ltc1871/ltc1871-1/ ltc1871-7 no r sense ? low quiescent current flyback, boost and sepic controller 2.5v v in 36v, burst mode ? operation

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